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CY28551-3
......................Document #: 001-05677 Rev. *D Page 6 of 28
Control Registers
10
Acknowledge from slave
10
Acknowledge from slave
18:11
Command Code – 8 bits
18:11
Command Code – 8 bits
19
Acknowledge from slave
19
Acknowledge from slave
27:20
Data byte – 8 bits
20
Repeated start
28
Acknowledge from slave
27:21
Slave address – 7 bits
29
Stop
28
Read
29
Acknowledge from slave
37:30
Data from slave – 8 bits
38
NOT Acknowledge
39
Stop
Table 4. Byte Read and Byte Write Protocol (continued)
Byte Write Protocol
Byte Read Protocol
Bit
Description
Bit
Description
Byte 0: Control Register 0
Bit
@Pup
Type
Name
Description
7
1
R/W
Reserved
6
1
R/W
PCIEX[T/C]6
PCIEX[T/C]6 Output Enable
0 = Disable (Tri-state), 1 = Enable
5
1
R/W
PCIEX[T/C]5
PCIEX[T/C]5 Output Enable
0 = Disable (Tri-state), 1 = Enable
4
1
R/W
PCIEX[T/C]4
PCIEX[T/C]4 Output Enable
0 = Disable (Tri-state), 1 = Enable
3
1
R/W
PCIEX[T/C]3
PCIEX[T/C]3 Output Enable
0 = Disable (Tri-state), 1 = Enable
2
1
R/W
PCIEX[T/C]2
PCIEX[T/C]2 Output Enable
0 = Disable (Tri-state), 1 = Enable
1
R/W
Reserved
0
1
R/W
SATA/PCIEX[T/C]0
SATA/PCIEX[T/C]0 Output Enable
0 = Disable (Tri-state), 1 = Enable
Byte 1: Control Register 1
Bit
@Pup
Type
Name
Description
7
1
R/W
SATA/DOT96]
SATA/DOT96Output Enable
0 = Disable (Tri-state), 1 = Enable
6
1
R/W
24_48M
24_48M Output Enable
0 = Disabled, 1 = Enabled
5
1
R/W
48M
48M Output Enable
0 = Disabled, 1 = Enabled
4
1
R/W
REF2
REF2 Output Enable
0 = Disabled, 1 = Enabled
3
1
R/W
REF1
REF1 Output Enable
0 = Disabled, 1 = Enabled
2
1
R/W
REF0
REF0 Output Enable
0 = Disabled, 1 = Enabled
1
R/W
CPU[T/C]1
CPU[T/C]1 Output Enable
0 = Disable (Tri-state), 1 = Enabled
0
1
R/W
CPU[T/C]0
CPU[T/C]0 Output Enable
0 = Disable (Tri-state), 1 = Enabled
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